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73S8010R Low Cost Smart Card Interface
DATA SHEET
January 2008
DESCRIPTION
The TERIDIAN 73S8010R is a single smart card interface IC. The TERIDIAN 73S8010R has been designed to provide full electrical compliance with ISO-7816-3 and EMV 4.0 (EMV2000) specifications. Interfacing with the host is done through the two-wire I2C bus, and one interrupt output to inform the system controller of the card presence and faults. The card clock signal can be generated by an on-chip oscillator using an external crystal, or by connection to a clock signal. The TERIDIAN 73S8010R incorporates an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage (3V or 5V), coming from an internal Low Drop-Out (LDO) voltage regulator. This LDO regulator is powered by a dedicated power supply input VPC. Digital circuitry is separately powered by a digital power supply VDD. With its embedded LDO regulator, the TERIDIAN 73S8010R is a cost-effective solution for any application where a 5V (typically -5% +10%) power supply is available. Hardware support for auxiliary I/O lines, C4 / C8 contacts, is provided. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a card over-current, a VDD (digital power supply), a VPC (regulator power supply), a VCC (card power supply) or an over-heating fault. The card over-current circuitry is a true current detection function, as opposed to VCC voltage drop detection, as usually implemented in ICC interface ICs. The VDD voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network. It allows automated card deactivation at a customized VDD voltage threshold value. It can be used, for instance, to match the system controller operating voltage range.
ADVANTAGES
* * * Single smart card interface IC firmware compatible with TDA8020 Traditional step-up converter is replaced by a LDO regulator:
Greatly reduced power dissipation Fewer external components are required Better noise performance High current capability (90mA supplied to the card)
* *
Small format (5x5x0.8mm) QFN32 package option True card over-current detection
FEATURES
* Card Interface: Complies with ISO-7816-3 and EMV 4.0 A LDO voltage regulator provides 3V / 5V to the card from an external power supply input Provides at least 90mA to the card ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry Protection includes 3 voltage supervisors that detects voltage drops on VCC card and on power supplies VDD and VPC The VDD voltage supervisor threshold value can be externally adjusted Over-current detection 150mA max. 1 card detection input Auxiliary I/O lines, for C4 / C8 contact signals CLK signal up to 20MHz Host Interface: Fast mode, 400kbps I2C slave bus 8 possible devices in parallel One control register and one status register Interrupt output to the host for fault detection Crystal oscillator or host clock, up to 27MHz Power Supply: VPC: 4.75V to 5.5V VDD: 2.7V to 5.5V 6kV ESD Protection on the card interface Package: SO28 or QFN32
*
APPLICATIONS
* * * * Set-Top-Box Conditional Access and Pay-perView Point of Sales & Transaction Terminals Control Access & Identification Multiple card and SAM reader configurations *
* *
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
FUNCTIONAL DIAGRAM
VDD
[20] 21
VDDF_ADJ
[17] 18
GND
[2] 5
VPC
[3] 6
[4, 5, 6, 9, 16, 25, 32] 7, 8, 9
NC
VPC FAULT
GND
[21] 22
VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE
[1] 4 VDD FAULT VCC FAULT
SCL
[18] 19
LDO REGULATOR & VOLTAGE SUPERVISORS
GND
[12] 14
GND
[15] 17
Int_Clk
SDA
[19] 20
R-C OSC.
VCC
SAD0 SAD1 SAD2 INT
[29] 1 [30] 2 [31] 3
I2C DIGITAL & FAULT LOGIC
ICC RESET BUFFER
[14] 16
RST
[22] 23
ISO-7816 SEQUENCER
ICC CLOCK BUFFER
[13] 15
CLK
[7] 10
XTALIN
[23] 24
PRES XTAL OSC
[24] 25
XTALOUT
CLOCK GENERATION
OVER TEMP
TEMP FAULT
[26] 26
[8] 11
IOUC
[27] 27
I/O
AUX1UC AUX2UC
[28] 28
ICC I/O BUFFERS
[11] 13
AUX1 AUX2
[10] 12
Pin numbers reference to the SO28 package [Pin numbers] reference to the QFN32 Package
Figure 1: 73S8010R Block Diagram
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
PIN DESCRIPTION
CARD INTERFACE
NAME I/O AUX1 AUX2 RST CLK PRES VCC GND PIN (SO) 11 13 12 16 15 10 17 14 PIN (QFN) 8 11 10 14 13 7 15 12 DESCRIPTION Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. Card reset: provides reset (RST) signal to card. Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by crystal oscillator frequency and CLKSEL bits in the control register. Card Presence switch: active high indicates card is present. Includes a pull-down resistor. Card power supply - logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. Card ground.
MISCELLANEOUS INPUTS AND OUTPUTS
NAME XTALIN XTALOUT VDDF_ADJ NC PIN (SO) 24 25 18 7, 8, 9 PIN (QFN) 23 24 17 4, 5, 6, 9, 16, 25, 32 DESCRIPTION Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock input. VDD threshold adjustment input: this pin can be used to overwrite higher VDDF value (that controls deactivation of the card). Must be left open if unused. Non-connected pin.
POWER SUPPLY AND GROUND
NAME VDD VPC GND GND GND PIN (SO) 21 6 4 14 5, 22 PIN (QFN) 20 3 1 12 2,21 DESCRIPTION System controller interface supply voltage and supply voltage for internal circuitry. LDO regulator power supply source. LDO regulator ground. Smart Card I/O Ground. Digital ground.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73S8010R Low Cost Smart Card Interface DATA SHEET
MICROCONTROLLER INTERFACE
PIN (SO) 23 1 2 3 PIN (QFN) 22 29 30 31
NAME INT SAD0 SAD1 SAD2
DESCRIPTION Interrupt output(negative assertion). Interrupt output signal to the processor. A 20k pull up to VDD is provided internally Serial device address bits. Digital inputs for address selection that allows for the connection of up to 8 devices in parallel. Address selections as follows: SAD2 0 0 0 0 1 1 1 1 SAD1 0 0 1 1 0 0 1 1 SAD0 0 1 0 1 0 1 0 1 I C Address (7 bits) 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh
2
Note: Pins SADO and SAD1 are internally pulled-down and SAD2 is internally pulled-up. The default address when left unconnected is 48h. SCL SDA I/OUC AUX1UC AUX2UC 19 20 26 27 28 18 19 26 27 28 I C clock signal input I C bi-directional serial data signal System controller data I/O to/from the card. Includes internal pull-up resistor to VDD System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD
2 2
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
SYSTEM CONTROLLER INTERFACE (I2C BUS)
A fast-mode 400kHz I2C bus slave interface is used for controlling the device and reading the status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This allows up to 8 devices to be connected in parallel. Device Address Selections SAD2 0 0 0 0 1 1 1 1 SAD1 0 0 1 1 0 0 1 1
2
SAD0 0 1 0 1 0 1 0 1
I2C Address (7 bits) 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh
Note: bit 0 of the I C address is the R/W bit. Refer to figures 2 and 3 for usage.
CONTROL register Power On Reset = 00h Name Start/Stop Warm reset 5Vand 3V Clock Stop Clock Stop Level Clksel1 Clksel2 I/O enable Bit 0 1 2 3 4 5 6 7 Description When set, initiates an activation and a cold reset procedure; when reset, initiates a deactivation sequence When set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute When set, VCC = 3v; when reset, VCC = 5v. When de-activating (setting bit 0 = 0) and operating with 3V (bit 2 =1), do not simultaneously set bit 2 =0. When set, the card clock is stopped. Bit 4 determines the card clock stop level When set, card clock stops high; when reset card clock stops low Bits 5 and 6 determine the clock rate to the. See card clock rate selection table for more details. I/O enable bit. When set, I/O is transferred on I/OUC; when reset I/O to I/OUC is high impedance.
Card clock rate selection table Bit Clksel2 0 0 1 1 Bit Clksel1 0 1 0 1 Card Clock Clkin/8 Clkin/4 Clkin/2 Clkin (Xtalin)
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73S8010R Low Cost Smart Card Interface DATA SHEET
I2C-bus Write to Control Register: I2C-bus Write command to the control register follows the format shown below. After the START condition, a slave address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode bit (R/W) - a `zero' indicates the master will write data to the control register. After the R/W bit, the 'zero' ACK bit is sent to the master by the device. The master now starts sending the 8 bits of data to the control register during the DATA bits. After the DATA bits, the `zero' ACK bit is sent to the master by the device. The master should send the STOP condition after receiving this ACK bit.
SDA
MSB SCL 1-7
LSB 8 9
MSB 1-8
LSB 9
START condition
ADDRESS bits
R/W bit
ACK bit
DATA bits
ACK bit
STOP condition
Figure 2 - I2C Bus Write Protocol STATUS register Power On Reset = 04h Name PRES PRESL I/O SUPL PROT Bit 0 1 2 3 4 Description Set when the card is present (pin PRES is high); reset when the card is not present. Set when the PRES pin changes state (rising/falling edge); reset when the status register is read. Generates an interrupt when set. Set when I/O is high; reset when I/O is low. Set when a voltage fault is detected; reset when the status register is read. Generates an interrupt when set Set when an over-current or over-heating fault has occurred during a card session; reset when the status register is read. Generates an interrupt when set Set during ATR when the card has not answered during the ISO 7816-3 time window (40000 card clock cycles); reset when the next session begins. Set during ATR when the card has answered before 400 card clock cycles; reset when the next session begin. Set when the card is active (VCC is on); reset when the card is inactive.
(c) 2005-2008 TERIDIAN Semiconductor Corporation
MUTE EARLY ACTIVE
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73S8010R Low Cost Smart Card Interface DATA SHEET
I2C-bus Read from Status Register: I2C-bus Read Command from the Status Register follows the format shown below. After the START condition, a slave address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode bit (R/W) - a `one' indicates the master will read data from the status register. After the R/W bit, the 'zero' ACK bit is sent to the master by the device. The device now starts sending the 8-bit status register data to the control register during the DATA bits. After the DATA bits, the `one' ACK bit is sent to the device by the master. The master should send the STOP condition after receiving the ACK bit.
SDA
MSB SCL 1-7
LSB 8 9
MSB 1-8
LSB 9
START condition
ADDRESS bits
R/W bit
ACK bit
DATA bits
ACK bit
STOP condition
Figure 3 - I2C Bus Read Protocol I2C-bus timing definition:
SDA Tbuf
SCL Thi
T lo w
T h d s ta
T sudat
Thddat
T s u s to
Figure 4 - I2C Bus Timing Definitions Symbol Fsclk Tlow Thi Thdsta Tsudat Thddat Tsusto Tbuf
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Parameter Clock frequency Clock low Clock high Hold time START condition Data set up time Data hold time Set up time STOP condition Bus free time between a STOP and START condition
Min. 1.3 0.6 0.6 100 5 0.6 1.3
Typ.
Max. 400
Unit kHz s s s ns ns s s
Rev 1.5
900
(c) 2005-2008 TERIDIAN Semiconductor Corporation
73S8010R Low Cost Smart Card Interface DATA SHEET
POWER SUPPLY AND VOLTAGE SUPERVISON
The TERIDIAN 73S8010R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller. Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card deactivation sequence is forced upon fault of any of these voltage supervisors. The two voltage supervisors for VPC and VCC are linked so that a fault is generated to activate a deactivation sequence when the voltage VPC becomes lower than VCC. It allows the 73S8010R to operate at lower VPC voltage when using 3V cards only. The voltage regulator can provide a current of at least 90mA on VCC that comply easily with EMV 4.0 specification. The VPC voltage supervisor threshold values are defined from EMV 4.0 standard. A third voltage supervisor monitors the VDD voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3V nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the QFN package) is used to connect an external resistor REXT to ground to raise the VDD fault voltage to another value VDDF. The resistor value is defined as follows: REXT= 56k /(VDDF - 2.33) An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as: Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas. R3 = 24000 / Kx R1 = R3*(Kx / (1 - Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives: Kx = (2.789 / 2.7) - 0.6125 = 0.42046. Solving for R3 gives: R3 = 24000 / 0.42046 = 57080. Solving for R1 gives: R1 = 57080 *(0.42046 / (1 - 0.42046)) = 41412. Using standard 1 % resistor values gives R3 = 57.6K and R1 = 42.4K. These values give an equivalent resistance of Kx = 0.4228, a 0.6% error. If the 2.3V default threshold is used, this pin must be left unconnected.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
CARD POWER SUPPLY
The card power supply is provided by the LDO regulator, and controlled by the digital ISO-7816-3 sequencer. Card voltage selection is carried out by bit 2 of the control register. Choice of the VCC capacitor: Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that the interface must be able to provide to the card are different. An external capacitor must be connected between the VCC pin and to the card ground in order to guarantee stability of the LDO regulator, and to handle the transient requirements. The type and value of this capacitor can be optimized to meet the desired specification. The table below shows the recommended capacitors for each VPC power supply configuration and applicable specification.
Specification Requirements Specification EMV 4.0 ISO-7816-3 Min VCC Voltage allowed during transient current 4.6V 4.5V Max transient current charge 30nA.s 20nA.s Min VPC Power Supply required 4.75V 4.75V
System Requirements Capacitor Type X5R/X7R w/ ESR < 100m Capacitor Value 3.3 F 1F
Table 1: Choice of VCC pin capacitor
OVER-TEMPERATURE MONITOR
A built-in detector monitors die temperature. Upon over-temperature condition (most likely resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is initiated, and a fault condition is reported to the system controller (sets bit 4 of the status register and generates an interrupt).
ON-CHIP OSCILLATOR AND CARD CLOCK
The TERIDIAN 73S8010R device has an on-chip oscillator that can generate the smart card clock using an external crystal, connected between the pins XTALIN and XTALOUT, to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. The card clock frequency may be chosen between 4 different division rates, defined by bits 5 and 6 of the I2C Control register, as per the following table: Bit Clksel2 0 0 1 1 Bit Clksel1 0 1 0 1
Card Clock Clkin/8 Clkin/4 Clkin/2 Clkin (Xtalin)
Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs bits 3 and 4 of the I2C Control register, respectively Clock Stop, and Clock Stop Level.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
ACTIVATION SEQUENCE
After Power on Reset, the signal INT is low until the VDD is stable. When VDD has been stable for approximately 10 ms and the signal INT is high, the system controller may read the status register to see if the card is present. If all the status bits are satisfied, the system controller can initiate the activation sequence by writing a `1' to Start/Stop bit (bit 0) of control register. The following steps show the activation sequence and the timing of the card control signals when the system controller initiates the Start/Stop bit (bit 0) of the control register: Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the session is aborted. Turn I/O to reception mode at the end of t1. CLK is applied to the card at the end of t2. RST (to the card) is set high at the end of t3.
Start/Stop
VCC IO CLK RST
t1
t2
t3
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator), I/O in reception mode t2 =1.5s, CLK starts t3 = >42000 card clock cycles, RST set high Figure 5 - Activation Sequence
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
DEACTIVATION SEQUENCE
Deactivation is initiated either by the system controller by resetting the Start/Stop bit, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VPC fault, VCC fault, and card extraction during the session. The following steps show the deactivation sequence and the timing of the card control signals when the system controller clears the start/stop bit: RST goes low at the end of t1. CLK goes low at the end of t2. I/O goes low at the end of t3. Out of reception mode. Shut down VCC at the end of time t4.
Start/Stop
RST CLK IO
VCC
t1
t2
t3
t4
t1 = t2 = t3 = t4 =
> .5s > 7.5s > .5s > .5s Figure 6 - Deactivation Sequence
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73S8010R Low Cost Smart Card Interface DATA SHEET
INTERRUPT
Interrupt is an active low interrupt. It is set low if any of these internal faults are detected: -VCC fault -VDD fault -VPC fault Or if one of these status bits condition is detected: -Early ATR -Mute ATR -Card insert or card extract -Protection status from Over-current or Over-heating In case the interrupt is set low by the detection of these status bits, then the interrupt is set high when these status bits are read. (READ STATUS DONE)
INT
ANY FAULT
STATUS BITS
READ STATUS DONE
Figure 7 - FAULT Functions, INT operation Note that a power-on-reset event will reset all of the control and status registers to their default states. A VDD fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that creates interval "t1," not clearing the interrupt until VDD is valid for at least t1. VDD fault can be considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of VDD fault, POR will be asserted.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
WARM RESET
The 73S8010R automatically asserts a warm reset to the card when instructed through the bit 1 of the I2C Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The bit Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
IO
Warm Reset (bit 1)
RST
t1
t2
t3
t1 > 1.5s, Warm Reset Starts t2 = 42000 card clock cycles, End of Warm Reset t3 = Resets Warm Reset bit 1 when detected ATR or Mute
Figure 8 - Warm Reset operation
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73S8010R Low Cost Smart Card Interface DATA SHEET
I/O CIRCUITRY AND TIMING
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the activation sequencer enables the I/O reception state. See Activation Sequence timing section for more details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable bit 7 of control register is set, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then both I/O lines return to their neutral state. The delay between these signals is shown in Figure 9.
IO
IOUC
tIO_HL
Delay from I/O to I/OUC: Delay from I/OUC to I/O:
tIO_LH
tIO_HL = 100ns tIOuc_HL = 100ns
tIOUC_HL
tIOUC_LH
tIO_LH = 25ns tIOUC_LH = 25ns
Figure 9 - I/O Timing Definition
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010C Low Cost Smart Card Interface DATA SHEET
TYPICAL APPLICATION SCHEMATIC
AUX2UC_to/from_uC AUX1UC_to.from_uC I/OUC_to/from_uC See note 7 See NOTE 3 SAD0 SAD1 SAD2 - OR C2 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R3 Rext2 Y1 CRYSTAL See NOTE 4 See NOTE 1 VDD C6 R1 Rext1 100nF R4 2K 73S8010R SO28 See note 6 INT_interrupt_to_uC SDA_to/from_uC VDD R2 NOTES: Card detection 1) VDD = 2.7V to 5.5V DC. 20K switch is normally closed 2) VPC = 4.75V(EMV, ISO) to 5.5V DC 3) Required if external clock from uP is used. 4) Required if crystal is used. Y1, C2 and C3 must be removed if external clock is used. 5) Optional. Can be left open. 6) R1 and R3 are external resistors that adjust the VDD fault voltage. Can be left open. 7) Hardware to define address of device ISO7816=1uF, EMV=3.3uF Low ESR (<100mohms) C1 should be placed near the SC connecter contact SCK_from_uC R5 2K 22pF C3 22pF External_clock_from uC See NOTE 5
VPC
C4 100nF
C5 10uF
See note 2
SAD0 SAD1 SAD2 GND GND VPC NC NC NC PRES I/O AUX2 AUX1 GND
AUX2UC AUX1UC I/OUC XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ VCC RST CLK
C1 10 9 SW-2 SW-1 8 7 6 5 4 3 2 1 C8 I/O VPP GND C4 CLK RST VCC
CLK track should be routed far from RST, I/O, C4 and C8.
Smart Card Connector
Figure 10: 73S8010R - Typical Application Schematic
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73S8010R Low Cost Smart Card Interface DATA SHEET
ELECTRICAL SPECIFICATION
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to the device. PARAMETER Supply Voltage VDD Supply Voltage VPC Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except card interface) Pin Voltage (card interface) ESD Tolerance - Card interface pins ESD Tolerance - Other pins RATING -0.5 to 6.0 VDC -0.5 to 6.0 VDC -0.3 to (VDD +0.5) VDC -60 to 150C -0.3 to (VDD +0.5) VDC -0.3 to (VCC + 0.5) VDC +/- 6kV +/- 2kV
Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage VDD Supply Voltage VPC Ambient Operating Temperature Input Voltage for Digital Inputs RATING 2.7 to 5.5 VDC 4.75 to 5.5 VDC -40C to +85C 0V to VDD + 0.3V
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET CHARACTERISTICS: CARD INTERFACE
SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Card Power Supply (VCC) Regulator General conditions, -40C < T < 85C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v Inactive mode Inactive mode ICC = 1mA Active mode; ICC <65mA; 5v Active mode; ICC <90mA; 5v Active mode; ICC <90mA; 3v Active mode; single pulse of 100mA for 2s; 5 volt, fixed load = 25mA Active mode; single pulse of 100mA for 2s; 3v, fixed load = 25mA Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5v Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 3v Static load current, VCC>4.6 or 2.7 volts as selected, -0.1 -0.1 4.60 4.55 2.80 4.6 3.2 5.25 0.1 0.4 5.25 V V V V V V
VCC
Card supply voltage including ripple and noise
2.76
3.2
V
4.6
5.25
V
2.76
3.2
V
ICCmax ICCF VSR VSF CF
Maximum supply current to the card ICC fault current VCC slew rate - Rise rate on activate VCC slew rate - Fall rate on de-activate External filter capacitor (VCC to GND)
90 100 150 0.05 0.06 3.3 0.08 0.08 5
mA mA
V/s V/s
CF = 3.3F on VCC CF = 3.3F on VCC
0.02 0.025 1
F
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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73S8010R Low Cost Smart Card Interface DATA SHEET
SYMBOL PARAMETER Condition MIN Typ. MAX UNIT
Interface Requirements - Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. VOH VOH VOL VIH VIH VIL VINACT ILEAK IIL ISHORTL ISHORTH Output level, high (I/O, AUX1, AUX2) Output level, high (I/OUC, AUX1UC, AUX2UC) Output level, low Input level, high (I/O, AUX1, AUX2) Input level, high (I/OUC, AUX1UC, AUX2UC) Input level, low Output voltage when outside of session Input leakage Input current, low Short circuit output current Short circuit output current IOH =0 IOH = -40A IOH =0 IOH = -40A IOL=1mA 0.9 VCC 0.75 VCC 0.9 VDD 0.75 VDD 1.8 1.8 -0.3 IOL = 0 IOL = 1mA VIH = VCC VIL = 0 For output low, shorted to VCC through 33 ohms For output high, shorted to ground through 33 ohms CL = 80pF, 10% to 90% For I/OUC, AUX1UC, AUX2UC, CL=50pF Output stable for >200ns Falling edge from master to slave measured at 50% point Rising edge from master to slave measured at 50% point 8 11 VCC+v0.1 VCC + 0.1 VDD+0.1 VDD + 0.1 0.3 VCC +0.30 VDD +0.30 0.8 0.1 0.3 10 0.65 15 15 V V V V V V V V V V A mA mA mA
tR, tF tIR, tIF RPU FDMAX TFDIO
Output rise time, fall times Input rise, fall times Internal pull-up resistor Maximum data rate Delay, I/O to I/OUC, I/OUC to I/O, AUX1 to AUX1UC, AUX1UC to AUX1, AUX2 to AUX2UC, AUX2UC to AUX2 Delay, I/O to I/OUC, I/OUC to I/O, AUX1 to AUX1UC, AUX1UC to AUX1, AUX2 to AUX2UC, AUX2UC to AUX2 Input capacitance
100 1 14 1 60 100 200
ns s k
MHz
ns
TRDIO CIN
25
90 10
ns pF
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
SYMBOL VOH VOL VINACT IRST_LIM ICLK_LIM tR, tF PARAMETER Output level, high Output level, low Output voltage when outside of session Output current limit, RST Output current limit, CLK Output rise time, fall time Condition IOH =-200A IOL=200A IOL = 0 IOL = 1mA MIN 0.9 VCC 0 Typ. MAX VCC 0.3 0.1 0.3 30 70 8 100 45 55 UNIT V V V V mA mA ns ns %
Reset and Clock for card interface, RST, CLK
CL = 35pF for CLK, 10% to 90% CL = 200pF for RST, 10% to 90% CL =35Pf, FCLK 20MHz
Duty cycle for CLK
CHARACTERISTICS: DIGITAL SIGNALS
SYMBOL VIL VIH VOL VOH ROUT |IIL1| VILXTAL VIHXTAL IILXTAL PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Pull-up resistor, INT Input Leakage Current Input Low Voltage - XTALIN Input High Voltage - XTALIN Input Current XTALIN GND < VIN < VDD -5 -0.3 0.7*VDD GND < VIN < VDD -30 Condition MIN -0.3 0.7*VDD IOL = 2mA IOH = -1mA VDD - 0.45 20 5 0.5 VDD+0.3 30 Typ. MAX 0.8 VDD + 0.3 0.45 UNIT V V V V k A V V A
Digital I/O except for OSC I/O
Oscillator (XTALIN) I/O Parameters
DC CHARACTERISTICS
SYMBOL IDD IPC PARAMETER Supply Current on VDD Supply Current on VPC VCC on, ICC=0 I/O, AUX1, AUX2=high Condition MIN Typ. 1.5 0.45 MAX 3.0 0.65 UNIT mA mA
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET CHARACTERISTICS I2C INTERFACE
SYMBOL SDA, SCL VIL VIH VOL CIN IIN TF TSP Input Low Voltage Input High Voltage Output Low Voltage Pin capacitance Output High Voltage Output fall time -0.3 0.7*VDD IOL = 3mA 0.3* VDD VDD + 0.3 0.40 10 250 50 V V V pF V ns ns PARAMETER Condition MIN Typ. MAX UNIT
IOH = -1mA VDD - 0.45 20 + 0.1*CL CL = 0 to 400pF Transition from valid Pulse width of spikes that are logic level to opposite suppressed level
VOLTAGE / TEMPERATURE FAULT DETECTION CIRCUITS
SYMBOL PARAMETER VDD fault (VDD Voltage supervisor threshold) VPC fault (VPC Voltage supervisor threshold) VCC fault (VCC Voltage supervisor threshold) Die over temperature fault Condition MIN Typ. MAX UNIT
VDDF VPCF VCCF TF
No external resistor on VDDF_ADJ pin VPC2.15 VCC - 0.2 4.20 2.5 115
2.4
V V
4.55 2.7 145
V V C
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
MECHANICAL DRAWING (QFN)
5 2.5
0 .8 5 N O M ./ 0 .9 M A X . 0 .0 0 / 0 .0 0 5 0 .2 0 R E F .
1 2 3
2.5 5
S E A T IN G PLANE
TOP VIEW
S ID E V IE W
0.35 / 0.45
3.0 / 3.75 0.18 / 0.3 1.5 / 1.875
CHAMFERED 0.30
1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.2 MIN. 0.35 / 0.45 0.5 0.5 0.25
BOTTOM VIEW
Figure 11: QFN 32
Page: 21 of 24
(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
PACKAGE PIN DESIGNATION (QFN)
CAUTION: Use handling procedures necessary for a static sensitive component
(Top View)
AUX2UC AUX1UC
I/OUC 26
SAD2
SAD1
NC
SAD0
32
31
30
29
28
27
GND GND VPC NC NC NC PRES I/O
1 2 3 4 5 6 7 8 10 11 12 13 14 15 AUX1 AUX2 CLK NC RST GND VCC NC 16 9
25 24 23 22
NC
XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ
TERIDIAN 73S8010R
21 20 19 18 17
Figure 12: QFN32 73S8010R Pin Out
Page: 22 of 24
(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
MECHANICAL DRAWING (SO)
.050 TYP. (1.270)
.305 (7.747) .285 (7.239) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076)
.420 (10.668) .390 (9.906)
.110 (2.790) .092 (2.336) .016 nom (0.40)
.335 (8.509) .320 (8.128)
Figure 13: 28 Lead SO
PACKAGE PIN DESIGNATION (SO)
CAUTION: Use handling procedures necessary for a static sensitive component
(Top View)
SAD0 SAD1 SAD2 GND GND VPC NC NC NC PRES I/O AUX2 AUX1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
AUX2UC AUX1UC I/OUC XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ VCC RST CLK
73S8010R
22 21 20 19 18 17 16 15
Figure 14: 28SO 73S8010R Pin Out
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R Low Cost Smart Card Interface DATA SHEET
ORDERING INFORMATION
PART DESCRIPTION 73S8010R -SOL 28-pin Lead-Free SO 73S8010R -SOL 28-pin Lead-Free SO Tape / Reel 73S8010R -QFN 32-pin Lead-Free QFN 73S8010R -QFN 32-pin Lead-Free QFNTape / Reel ORDER NO. 73S8010R -IL/F 73S8010R -ILR/F 73S8010R -IM/F 73S8010R -IMR/F PACKAGING MARK 73S8010R -IL 73S8010R -IL 73S8010R 73S8010R
Data Sheet
This final data sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance.
TERIDIAN Semiconductor Corp. * 6440 Oak Canyon, Suite 100 * Irvine, CA * 92618-5201 TEL (714) 508-8800 * FAX (714) 508-8877
http://www.teridian.com 01/17/08 Rev 1.5
Page: 24 of 24
(c) 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5

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